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Subject: architecture, design reuse, linked data, ontology, system on chip


Year: 2006


Type: Proceedings



Title: Improving HDL Higher Level Logical Analysis Using Boolean Function Feature


Author: Zdraveski, Vladimir
Author: Dimitrovski, Andrej
Author: Trajanov, Dimitar



Abstract: Increased designers' interest in digital system design using hardware description languages has resulted in a huge data set of open source, available on the Web. Difficulties in discovering specific component introduce the need of automation in the process of search and reuse of already existing components. Despite the interface, a very important part required for a complete automation is the software analysis of the components' inner architecture. Applying the Semantic Web methodologies and using our existing hardware description ontology, we propose extension that will enable a semantic annotation of the inner architecture and will significantly improve the tools for automatic search and system composition of existing components. The ontology is published and can be used as a model for a standardized annotation, in order to increase the availability of the existing components and to provide easier reuse in novel designs. The concept is also applicable inside a company, to accelerate the retrieval through the local repositories of components.


Publisher:


Relation: TELFOR 2006, Belgrade, Serbia



Identifier: oai:repository.ukim.mk:20.500.12188/25106
Identifier: http://hdl.handle.net/20.500.12188/25106



TitleDateViews
Improving HDL Higher Level Logical Analysis Using Boolean Function Feature200633