Subject: memory, superscalar, processor, register renaming, shelving, out of order, simulation
Year: 2000
Type: Proceedings
Title: Reducing the number of instructions
Author: Gushev, Marjan
Author: Mishev, Anastas
Author: Popovski, G
Author: Mitrevski, P
Abstract: The purpose of this article is to reduce the number of instructions while executing in processor. We analyse memoiy address dependent instructions and eliminate the ada'ress generation processing if the address was previously calculated For standard RISC? WIWand inorder superscalar processor we introduce a solution where the MI (Reduction of Memory Instructions) Algorithm is perfomzed in the compile stage and aa'hess dependent instructions do not enter the processor at all. For out-qfdr&r superscalm processors we introduce two solutions, theJirst one when these instructions me not issued at all and the second solution when these instructions are issued only in a reservation station without execution unit. All these solutions improve the behaviour of thc processor for at least 10% since the processor does not executes these instructions.
Publisher: IEEE
Relation: ITI 2000. Proceedings of the 22nd International Conference on Information Technology Interfaces (Cat. No. 00EX411)
Identifier: oai:repository.ukim.mk:20.500.12188/24199
Identifier: http://hdl.handle.net/20.500.12188/24199
